NAND flash memories are reaching the limit of miniaturization, and hence there has been demanded a novel memory technology in which intercell interference is small and which is suitable for miniaturization and realization of a high capacity. As a candidate for this technology, studies and development of a resistance change memory have been positively advanced.
In a memory cell array of the resistance change memory, a crosspoint structure in which a resistance change element is connected to a diode element (an element that exhibits non-ohmic current-voltage characteristics) in series at an intersecting portion of two conductive lines is often adopted. That is because the high capacity of the crosspoint structure can be readily achieved by providing a three-dimensional memory cell array.
Here, as one technical candidate for the diode element, a punch-through diode having a semiconductor stacked structure of n/p/n or p/n/p has been considered. However, the conventional punch-through diode has an operation system that each layer has a large thickness, neutral regions remain in some of elements under zero bias or a low voltage, and all layers are completely depleted under a high voltage. Therefore, when this structure is applied as a diode element in the resistance change memory as it is, since a thickness of the diode element is too large, this structure is not suitable for the resistance change memory that has a three-dimensional structure as a premise.
On the other hand, when a thickness of each layer in the punch-through diode is reduced, all the layers are completely depleted even under zero bias or a low voltage, and a problem occurs in a memory cell selecting function required in the diode element in the resistance change memory. That is, in this case, an OFF current (a leak current flowing through half-selected memory cells) is increased.